Imaging devices, including charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) imagers, are commonly used in photo-imaging applications.
A CMOS imager circuit includes a focal plane array of pixels, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A typical four transistor (4T) CMOS imager pixel 10 is shown in FIG. 1. The pixel 10 includes a photosensor 12 (e.g., photodiode, photogate, etc.), transfer transistor 14, floating diffusion region FD, reset transistor 16, source follower transistor 18 and row select transistor 20. The photosensor 12 is connected to the floating diffusion region FD by the transfer transistor 14 when the transfer transistor 14 is activated by a transfer gate control signal TX.
The reset transistor 16 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa_pix. A reset control signal RST is used to activate the reset transistor 16, which resets the floating diffusion region FD to the array pixel supply voltage Vaa_pix level as is known in the art.
The source follower transistor 18 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa_pix and the row select transistor 20. The source follower transistor 18 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 20 is controllable by a row select signal SEL for selectively connecting the source follower transistor 18 and its output voltage signal Vout to a column line 22 of a pixel array.
A typical CMOS imager 50 is illustrated in FIG. 2. The imager 50 includes a pixel array 52 connected to column sample and hold (S/H) circuitry 54. The pixel array 52 comprises a plurality of pixels arranged in a predetermined number of rows and columns. In operation, the pixels of each row in the array 52 are all turned on at the same time by a row select line and the pixels of each column are selectively output on a column line. A plurality of row and column lines are provided for the entire array 52.
The row lines are selectively activated by row decoder and driver circuitry (not shown) in response to an applied row address. Column select lines are selectively activated by column decoder 56 and driver circuitry contained within the column sample and hold circuitry 54 in response to an applied column address such that the signal on the column lines are sequential sampled and readout. Thus, a row and column address is provided for each pixel. The CMOS imager 50 is operated by a control circuit (not shown), which controls the row and column circuitry for selecting the appropriate row and column lines for pixel readout.
The CMOS imager 50 illustrated in FIG. 2 uses a dual channel readout architecture. That is, the imager 50 includes a first path (designated as G1/G2) and a second path (designated as RJB) for pixel and reset signals readout from the column lines of the array 52. Each readout path G1/G2, R/B is respectfully used to readout half the pixels connected to the column S/H circuitry 54. The first path G1/G2 outputs analog reset and pixel signals associated with green pixels while the second path R/B outputs analog reset and pixel signals associated with red or blue pixels depending on the row which is read. The pixel array 52 uses the well known Bayer pattern in which alternating rows of pixels are either alternating green and red pixel or alternating green and blue pixels.
Once readout, the green analog reset and pixel signals pass through an amplifier (PGA) 58 and an analog-to-digital converter (ADC) 62 before being processed as digital signals by a digital block 66. Amplifier 58 and ADC 62 comprise a green port of the imager 50. Once readout, the blue or red analog reset and pixel signals (depending on the row being read) pass through an amplifier (PGA) 60 and an analog-to-digital converter (ADC) 64 before being processed as digital signals by the digital block 66. Amplifier 60 and ADC 64 comprise a red/blue port of the imager 50.
The operational speed of the above-described readout circuitry is limited by processing constraints particularly as the size of the array 52 increases. In addition, attempts to speed up the circuitry may introduce undesirable noise into the readout process. Parallel readout architecture has been suggested in which the columns of an array row are read by more than the two analog-to-digital converters 62, 64, however, employing additional analog-to-digital converters operating in parallel may create a boundary effect due to the mismatch of gain and offset between adjacent readout channels. If the gain or offset of two readout channels are different, under uniform light the signals of the two adjacent columns readout by parallel analog-to-digital converters may create what appears to be an amplitude shift. The shift in amplitude may cause a boundary effect (e.g., one side of the image to be brighter than the other). Accordingly, there is a need and desire to increase the operational speed of the readout path circuitry while mitigating the possibility of boundary effects.